In recent years, a ferroelectric memory (FeRAM) has been drawing attention, as a nonvolatile memory that can hold information even when power supply is cut off. The FeRAM utilizes hysteresis characteristics of a ferroelectric to store information. In the ferroelectric memory, a ferroelectric capacitor is provided in each memory cell. In a ferroelectric capacitor, a ferroelectric film is provided as a capacitor dielectric between a pair of electrodes. A ferroelectric capacitor becomes polarized in accordance with an applied voltage between the pair of electrodes, and its spontaneous polarization remains even though the applied voltage is removed, whereby information can be held. When the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. The spontaneous polarization enables can be detected to read information.
In addition, because the capacitance of the ferroelectric film is larger than that of SiO2, a ferroelectric capacitor may be integrated in a boosting circuit or a smoothing circuit. A bottom electrode, a ferroelectric film, and a top electrode of a ferroelectric capacitor integrated in the boosting circuit or the smoothing circuit are all larger in size than those of a ferroelectric capacitor incorporated in the memory cell. Therefore, a great number of contact holes are formed on the bottom electrode.
Here, a conventional method of manufacturing a semiconductor device having a peripheral circuit including a ferroelectric capacitor will be explained. FIGS. 18A and 18B to FIGS. 20A and 20B are diagrams illustrating a conventional method of manufacturing a semiconductor device. FIGS. 18B, 19B, and 20B are cross-sectional views taken along the line II-II in FIGS. 18A, 19A, and 20A, respectively.
To manufacture such a semiconductor device (ferroelectric memory), an element such as a CMOS transistor is first formed on a semiconductor substrate, e.g., an Si substrate; then, an interlayer insulating film, wirings, and the like are formed, and then, as shown in FIGS. 18A and 18B, an alumina film 111 is formed as an adhesion layer (base film) of a ferroelectric capacitor. Next, a conductive film for a bottom electrode (a bottom electrode film) and a ferroelectric film are sequentially formed on the alumina film 111. A Pt film is formed as the bottom electrode film, and a Pb(Zr,Ti)O3 film (a PZT film) is formed as the ferroelectric film. Next, the ferroelectric film is crystallized by heat treatment. Thereafter, an IrOx film is formed as a conductive film for a top electrode (a top electrode film) on the ferroelectric film. Next, by processing the top electrode film, the ferroelectric film, and the bottom electrode film in that order, a plurality of ferroelectric capacitors (not shown) are formed in an area in which an FeRAM cell array is to be formed, and, as shown in FIGS. 18A and 18B, a bottom electrode 115, a PZT film 116, and a top electrode 117 are formed in an area in which a peripheral circuit including a boosting circuit and a smoothing circuit is to be formed.
In addition, a planar shape of each of the bottom electrodes 115 is a rectangle having a narrow side of 50 μm to 60 μm in length and a longitudinal side of 200 μm to 250 μm in length. Meanwhile, a planar shape of the bottom electrode in the ferroelectric memory cell array is a rectangle having a narrow side of 4.0 μm in length and a longitudinal side of 560 μm in length.
After processing these films, a TEOS oxide film 118 is formed as an interlayer insulating film and flattened through CMP (Chemical Mechanical Polishing) Next, in the TEOS oxide film 118, the alumina film 111, and the like, contact holes (not shown) are formed to reach a diffusion layer (semiconductor substrate) or the like formed below the bottom electrode 115. Thereafter, as shown in FIGS. 19A and 19B, contact holes 121 that reach the bottom electrode 115 and contact holes 122 that reach the top electrode 117 are formed in the TEOS oxide film 118. In this situation, a plurality of contact holes 121 are formed for each of the bottom electrodes 117.
Next, on the entire surface, a TiN film (about 150 nm) as a lower barrier metal film, an Al film, and a TiN film as an upper-barrier metal film are formed and patterned to form a wiring 125 connected through all of the contact holes 121 to the bottom electrode 115 and a wiring 126 connected through the contact holes 122 to the top electrode 117, as shown in FIGS. 20A and 20B.
In addition, also in the ferroelectric memory cell array section, wirings are formed concurrently with the peripheral circuit section.
Next, after forming an interlayer insulating film that covers the wirings 125 and 126, heat treatment for eliminating moisture in the interlayer insulating film is implemented for 60 minutes, in the presence of N2 at 350° C.
Thereafter, by further forming wirings, interlayer insulating films, and the like, a semiconductor device is completed.
However, when the inventor of the present invention actually observed a surface of a semiconductor device that was produced in accordance with the conventional method as described above, a recess-like defect was found in the vicinity of the contact portion of the bottom electrode for the peripheral circuit section. Such a defect as described above was not found in the memory cell array section. In order to identify what the defect was, the inventor carried out cross-sectional observation and composition analysis. FIGS. 21A to 21C are graphs representing the results of the composition analysis on a wiring in the vicinity of the contact portion. In the cross-sectional observation, it was found that discoloration in the wiring had occurred in the vicinity of the contact portion of the bottom electrode. Moreover, as shown in FIGS. 21A to 21C, peaks of Si and Pt appeared in the region where, in a normal situation, a peak of Al would conspicuously emerge. This fact suggests that, due to reaction, these atoms diffused into the wiring.
Meanwhile, in a semiconductor device including a ferroelectric capacitor, in order to improve the characteristics of the ferroelectric film, annealing processing in the presence of oxygen after formation of the top electrode is requisite. Therefore, as a material for the electrode, an oxidization-proof material, or a material that maintains electrical conductivity even when being oxidized, has been utilized. As the foregoing material, metal of the platinum family or oxide thereof, such as Pt, Ir, or IrOx, is mainly utilized. As another material for the wiring, Al is utilized, which is generally used even in other kind of semiconductor devices. The ferroelectric capacitor is connected through Al wirings to other elements or the like. In this situation, the thickness of the ferroelectric film is relatively large, and the dimension of the capacitor in the vertical direction is also relatively large. Therefore, a contact hole to the capacitor electrode is likely to be deep. An Al wiring is formed through the deep contact hole.
However, it is known that contact between Al and platinum-family metal such as Pt causes eutectic reaction; as disclosed in specifications of Japanese Patents No. 3045928 and No. 3165093, it is necessary to form between them a barrier metal film such as a TiN film. In other words, as shown in FIG. 22, a ferroelectric capacitor having a bottom electrode 148 made of Pt is formed on an insulating film 145, and an insulating film 146 is formed in such a way as to cover the ferroelectric capacitor. In the insulating film 146, a contact hole reaching the bottom electrode 148 is formed, and a barrier metal film 151 and a wiring 152 that are connected through the contact hole to the bottom electrode 148 are formed on the insulating film 146. The barrier metal film 151 and the wiring 152 are made of TiN and Al, respectively.
However, crystals of Pt and TiN are oriented in the same direction; therefore, if heat treatment is implemented after the Al wiring is formed on the TiN barrier metal film, Pt may pass through the TiN barrier metal film and react with Al. If the reaction such as this occurs, not only contact defect is caused, but also upward elevation occurs, whereby wirings in further upper layers may be affected.
Although, in logic products, a stacked barrier metal film formed by stacking a TiN film on a Ti film is usually utilized, in a ferroelectric capacitor, a Ti film absorbs O2 from a platinum-family metal oxide used as the electrode, at the contact interface, whereby a TiOx layer is formed. Consequently, contact resistance becomes higher. Japanese Patent Application Laid-Open No. 2002-100740 describes a stacked barrier metal film having a Ti film formed on a TiN film. However, the structure causes Ti and Al to react and generate electromigration.
[Patent Document 1]
Specification of Japanese Patent No. 3045928
[Patent Document 2]
Specification of Japanese Patent No. 3165093
[Patent Document 3]
Japanese Patent Application Laid-Open No. 2002-100740